Sub-nanosecond, multi-channel time digitizer

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  • Project title
    LAT-SINPLEX
  • Project status
    Delivered
  • Project type
    Design under contract
  • Client
    cosine
  • Target application
    Single-photon counting laser ranging and altimetry

The LAT-SINPLEX is an embedded system designed for a novel scientific instrument prototype, with the purpose of measuring the time between pulses with sub-nanosecond (currently at 27 ps) time resolution.

The system makes use of a commercial high-performance FPGA module, which includes an on-chip PowerPC processing core and DDR memory, capable of executing complex real-time processing algorithms on the input data. The FPGA module is attached to a custom carrier board, designed and produced by Logikon Labs specifically for the needs of our client. The complete system, with the FPGA module attached, measures just 115 mm x 75 mm x 15 mm (WxDxH) and consumes less than 3 Watts when fully operational.

The carrier board provides two 50 Ω-terminated coaxial inputs, which are connected to a high precision mixed-signal time digitizer ASIC. The FPGA contains custom on-chip digital circuitry for control and readout of the ASIC, while the PowerPC performs the actual time-of-flight calculation and provides an external interface for control of the system.

The LAT-SINPLEX can be controlled over USB and SPA-1 (Space Plug-and-Play Avionics over I2C). The USB interface is suitable for most laboratory applications, while the SPA-1 interface provides a standard way of interfacing the instrument with an on-board satellite computer. Reconfiguration of both the FPGA and the PowerPC software is possible via USB, as well as via an industry-standard JTAG interface.

The LAT-SINPLEX is a very versatile time digitizer, able to perform valuable scientific measurements in a variety of experiments. Potential applications include time-of-flight calculations for laser ranging and altimetry, as well as ultrasonic probes and various other high-precision measurements in physics. The reconfigurable FPGA and the software running on the on-chip PowerPC core can be reprogrammed to meet any other processing needs.


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Phase A

Phase B